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1 of 21 proprietary and confidential GS6042 final data sheet rev. 3 pds-060055 may 2014 gennum products GS6042 6g uhd-sdi/3g/hd/sd adaptive cable equalizer www.semtech.com key features ? supports data rates from 125mb/s to 6.25gb/s ? smpte st 2081 (proposed), smpte st 424, smpte st 292, and smpte st 259 compliant ? automatic cable equalization ? typical equalized length of belden 1694a cable: ? 80m at 5.94gb/s ? 210m at 2.97gb/s ? 300m at 1.485gb/s ? 500m at 270mb/s ? supports dvb-asi at 270mb/s ? supports madi at 125mb/s ? manual bypass control ? programmable carrier detect with squelch threshold adjustment ? automatic power-down on loss of signal ? differential output suppor ts dc-coupling from +1.2v to +3.3v cml logic ? optional 6db flat band gain on input ? selectable output de-emphasis: 2db, 6db, and 8db ? standard eia/jedec logic for control/status signals ? single +3.3v power supply operation ? 180mw power consumption (35mw in sleep) ? operating temperature range: - 40oc to +85oc ? small footprint qfn package (4mm x 4mm) ? footprint compatible with the gs2974a, gs2974b, gs2984, gs2994, and gs3440 ? pb-free and rohs compliant applications ? smpte st 2081 (proposed), smpte st 424, smpte st 292, and smpte st 259 coaxial cable serial digital interfaces ? serialized 8b/10b encoded video streams up to 6.25gb/s description the GS6042 is a high-speed bicmos device designed to optimally equalize and restore signals received over 75 coaxial cable. the device supports data rates up to 6.25gb/s while being optimized for the proposed smpte st 2081, as well as smpte st 424, smpte st 292, and smpte st 259. the GS6042 features dc restoration to compensate for the dc content of smpte pathological signals. the carrier detect output pin (cd ) indicates whether an input signal has been dete cted. it can be connected directly to the sleep pin to enable automatic sleep on loss of input. a cd threshold is set via the sq_adj pin, allowing the GS6042 to distinguish betwee n small amplitude sdi signals and noise at the in put of the device. the equalizing and dc restore stages are disengaged and no equalization occurs when the bypass pin is high. this is useful for signals launched at the signal source with low data rates and/or sl ow rise/fall times. the GS6042 features a gain se lection pin (gain_sel) which can be used to compensate for 6db flat attenuation prior to the input of the device. the differential output can be dc-coupled to semtechs reclockers and cable drivers, as well as industry-standard cml logic by changing th e voltage applied to the vcc_o pin. in general, dc-c oupling to any termination voltage between +1.2v an d +3.3v is supported. the GS6042 also features programmable output de-emphasis with three user-selectable operating levels to support long pcb traces at the output of the device. power consumption of the GS6042 is typically 180mw when its output is dc-coupled at +1.2v. the GS6042 is pb-free, and the encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous subcomponents are rohs compliant.
GS6042 final data sheet rev. 3 pds-060055 may 2014 2 of 21 proprietary and confidential www.semtech.com GS6042 functional block diagram revision history version eco pcn date changes and/or modifications 3 019547 may 2014 corrected the values for the de-emphasis levels 2 017789 february 2014 converted to final data sheet. modified section 4.3 . included reference to 6g smpte standard. 1 016407 november 2013 converted to final data sheet. included information on 6.25g support. updated jitter characteristics. updates throughout. 0 012658 june 2013 new document equalizer output agc sdi sleep ddo bypass cd sdi ddo agc agc sq_adj squelch adjust carrier detect mute dc restore vcc_o vee_o op_ctl vcc_a vee_a gain_sel
GS6042 final data sheet rev. 3 pds-060055 may 2014 3 of 21 proprietary and confidential www.semtech.com contents key features................................................................................................................... ........................................1 applications ................................................................................................................... ........................................1 description .................................................................................................................... .........................................1 revision history ............................................................................................................... .....................................2 1. pin out..................................................................................................................... ............................................4 1.1 GS6042 pin assignment ..................................................................................................... ..............4 1.2 GS6042 pin descriptions ................................................................................................... ...............4 2. electrical characteristics.................................................................................................. ..............................6 2.1 absolute maximum ratings .................................................................................................. .........6 2.2 dc electrical characteristics ............................................................................................. ..............6 2.3 ac electrical characteristics ............................................................................................. ...............8 3. input/output circuits....................................................................................................... ........................... 10 4. detailed description........................................................................................................ ............................ 11 4.1 serial digital inputs ..................................................................................................... .................... 11 4.2 automatic (adaptive) cable equalization .............................................................................. 11 4.3 differential digital data output .......................................................................................... ....... 11 4.4 programmable squelch adjust (sq_adj) ............................................................................... 12 4.5 carrier detect, sl eep, and auto-sleep ..................................................................................... .13 4.6 gain_sel .................................................................................................................. .......................... 13 4.7 adjustable output swing, de-emphasis, and mute ........................................................... 14 5. application information..................................................................................................... ........................ 16 5.1 high-gain adaptive cable equalizers ...................................................................................... 1 6 5.2 pcb layout ................................................................................................................ ......................... 16 5.3 typical application circuit ............................................................................................... ............ 17 6. package & ordering information .............................................................................................. .............. 18 6.1 package dimensions ........................................................................................................ .............. 18 6.2 packaging data ............................................................................................................ .................... 18 6.3 recommended pcb footprint ................................................................................................. ... 19 6.4 marking diagram ........................................................................................................... .................. 19 6.5 solder reflow profiles .................................................................................................... ................ 20 6.6 ordering information ...................................................................................................... ............... 20
GS6042 final data sheet rev. 3 pds-060055 may 2014 4 of 21 proprietary and confidential www.semtech.com 1. pin out 1.1 GS6042 pin assignment figure 1-1: GS6042 pin out 1.2 GS6042 pin descriptions ground pad (bottom of package) GS6042 16-pin qfn (top view) sq_adj agc vcc_o sleep vcc_a bypass 5678 16 15 14 13 agc gain_sel vee_a sdi 1 2 3 4 sdi vee_o ddo ddo op_ctl 12 11 10 9 cd table 1-1: GS6042 pin descriptions pin number name type description 1 vee_a power most negative power supply connection for the input buffer, core, and control circuits. connect to ground. 2, 3 sdi, sdi input serial digital differential input. 4gain_selinput flat band gain control. please refer to the dc electrical characteristics table for logic level threshold and compatibility. this pin is a +2.5v input that is tolerant to +3.3v levels. when high, the device compensates for an additional 6db of loss across the entire operating band. this pin has an internal pull-down resistor. 5, 6 agc, agc external agc capacitor connection. 7bypassinput eq bypass control. please refer to the dc electrical characteristics table for logic level threshold and compatibility. this pin is a +2.5v input that is tolerant to +3.3v levels. forces the equalizer and dc-restore stages into bypass mode when high. no equalization occurs in this mode. this pin has an internal pull-down resistor.
GS6042 final data sheet rev. 3 pds-060055 may 2014 5 of 21 proprietary and confidential www.semtech.com 8sq_adjinput squelch threshold adjust. adjusts the input signal amplitude threshold of the carrier detect function. the serial data output of the device can be muted when the serial data input signal amplitude is too low by connecting the cd and op_ctl pins using a suitable resistor network (see figure 4-4 and figure 4-5 ). this pin has an internal pull-down resistor. note: the sq_adj function is only available when the device is not configured for auto-sleep mode. reference section 4.5 for more detail. 9op_ctlinput output swing, de-emphasis and mute control. when this pin is connected to gnd, the output swing is 850mv ppd with no de-emphasis applie d to the output signal. with this pin connected to +2.5v, the output is muted. intermediate voltages and functions are shown in table 4-5 . these voltages can be achieved as shown in figure 4-4 and figure 4-5 . this pin has an internal pull-down resistor. 10, 11 ddo , ddo output serial digital differential output. 12 vee_o power most negative power supply connection for the output buffer. connect to ground. 13 vcc_o power most positive power supply connection for the output buffer. connect to 1.2v - 3.3v dc. 14 sleep input sleep control. please refer to the dc electrical characteristics table for logic level threshold and compatibility. this pin is a +2.5v input that is tolerant to +3.3v levels. when high the part is powered-down except for the carrier detect function. this pin can be connected directly to the cd pin to automatically put the device to sleep (low-power operation) on loss of carrier. this pin has an internal pull-down resistor. note : when sleep is connected to cd for automatic power reduction on loss of carrier, the sq_adj pin will not modify the cd threshold. the cd threshold will revert to the default value used when sq_adj is pulled low. 15 cd output carrier detect status output. please refer to the dc electrical characteristics table for logic level threshold and compatibility. this pin is a +2.5v output. indicates presence of an input signal. when the cd pin is low, a signal has been detected at the in put. when this pin is high, this indicates loss of input signal. 16 vcc_a power most positive power supply connection for the input buffer, core and control circuits. connect to +3.3v dc. center pad power internally bonded to vee_a. connect to gnd with at least 5 vias. table 1-1: GS6042 pin descri ptions (continued) pin number name type description
GS6042 final data sheet rev. 3 pds-060055 may 2014 6 of 21 proprietary and confidential www.semtech.com 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value supply voltage - core/output driver -0.5v to +3.6v dc input esd voltage (hbm) 5kv storage temperature range (t s ) -50c to +125c input voltage range (any input) -0.3 to (v cc_a +0.3)v operating temperature range -40c to +85c solder reflow temperature 260c note: absolute maximum ratings are those va lues beyond which damage may occur. functional operation outside of the ranges shown in the ac and dc electrical characteristics is not guaranteed. table 2-2: dc electrical characteristics v cc_a = +3.3v 5%, t a = -40c to +85c, unless otherwise shown. parameter symbol conditions min typ max units notes supply voltage - core v cc_a 3.135 3.3 3.465 v supply voltage - output driver v cc_o 1.14 1.2 1.26 v 1 2.375 2.5 2.625 v 1 3.135 3.3 3.465 v 1
GS6042 final data sheet rev. 3 pds-060055 may 2014 7 of 21 proprietary and confidential www.semtech.com power consumption p d v cc_o = 1.2v v ddo = 425mv ppd 180 mw 2 v cc_o = 1.2v v ddo = 850mv ppd 195 mw 2 v cc_o = 2.5v v ddo = 425mv ppd 196 mw 2 v cc_o = 2.5v v ddo = 850mv ppd 221 mw 2 v cc_o = 3.3v v ddo = 425mv ppd 202 mw 2 v cc_o = 3.3v v ddo = 850mv ppd 240 mw 2 sleep mode sleep = high 35mw supply current - core i s 55ma 2 , 3 supply current - output driver i out v ddo = 850mv ppd 20ma 2 v ddo = 425mv ppd 10ma 2 input common mode voltage v cmin 1.7v output common mode voltage v cmout refer to section 4.3 cd output voltage logic levels v cd (oh) signal not present 2.0 v v cd (ol) signal present 0.4 v input voltage logic levels: gain_sel, bypass, sleep v ih minimum to assert 1.7 v 4 v il maximum to de-assert 0.7 v 4 notes: 1. v cc_o operates from +1.2v through +3.3v (+/-5%). 2. de-emphasis off. 3. an additional 3ma when de-emphasis is enabled. 4. gain_sel, bypass, sleep pins are +2.5v, but +3.3v tolerant. table 2-2: dc electrical characteristics (continued) v cc_a = +3.3v 5%, t a = -40c to +85c, unless otherwise shown. parameter symbol conditions min typ max units notes
GS6042 final data sheet rev. 3 pds-060055 may 2014 8 of 21 proprietary and confidential www.semtech.com 2.3 ac electrical characteristics table 2-3: ac electrical characteristics v cc_a = +3.3v 5%, t a = -40c to +85c, unless otherwise shown parameter symbol conditions min typ max units notes serial input data rate dr ddo 125 6250 mb/s 1 input voltage swing v sdi differential, 270mb/s and 1.485gb/s 720 800 950 mv ppd 2 differential, 2.97gb/s and 5.94gb/s 720 800 880 mv ppd 2 output voltage swing v ddo 100 differential load, op_ctl set for high swing 700 850 1000 mv ppd 100 differential load, op_ctl set for low swing 350 425 500 mv ppd output jitter at various cable lengths and data rates 6.25gb/s belden 1694a: 0-50m 0.35 ui 4 , 5 5.94gb/s belden 1694a: 0-80m 0.35 0.5 ui 4 , 5 2.97gb/s belden 1694a: 0-100m 0.2ui 3 , 4 , 5 2.97gb/s belden 1694a: 100-150m 0.3ui 3 , 4 , 5 2.97gb/s belden 1694a: 150-170m 0.4ui 3 , 4 , 5 2.97gb/s belden 1694a: 170-200m 0.5ui 3 , 4 , 5 2.97gb/s belden 1694a: 210m 0.5 ui 4 , 5 1.485gb/s belden 1694a: 0-200m 0.2ui 3 , 4 , 5 1.485gb/s belden 1694a: 200-260m 0.3ui 3 , 4 , 5 1.485gb/s belden 1694a: 260-300m 0.3 ui 4 , 5 270mb/s belden 1694a: 0-300m 0.1 0.15 ui 3 , 4 , 5 270mb/s belden 1694a: 300-500m 0.25 ui 3 , 4 , 5
GS6042 final data sheet rev. 3 pds-060055 may 2014 9 of 21 proprietary and confidential www.semtech.com output rise/fall time t r , t f 5.94gb/s, 2.97gb/s, and 1.485gb/s 20% - 80% 75ps 270mb/s 20% - 80% 150 ps mismatch in rise/fall time t r ,, t f 30ps duty cycle distortion 30 ps overshoot 10 % input return loss 5mhz - 1.485ghz 15 db 1.485ghz - 2.97ghz 10 db input resistance single-ended 1.9 k input capacitance single-ended 1.3 pf output resistance single-ended 50 notes: 1. device performance is optimized for standard data rates ( sd = 270mb/s, hd = 1.485gb/s, 3g = 2.970gb/s, 6g = 5.94gb/s). 2. 0m cable length. 3. all parts are production tested. in order to guarantee maximum jitter over the full range of specification (v cc_a = +3.3v 5%, t a = -40c to +85c, and 720-880mv pp launch swing from the sdi cable driver), the recommended applications circuit must be used. 4. based on validation data using the re commended applications circuit, with v cc_a = +3.3v, t a = -40c to +85c and 800mv pp launch swing from the sdi cable driver. 5. gain_sel = 0. table 2-3: ac electrical ch aracteristics (continued) v cc_a = +3.3v 5%, t a = -40c to +85c, unless otherwise shown parameter symbol conditions min typ max units notes
GS6042 final data sheet rev. 3 pds-060055 may 2014 10 of 21 proprietary and confidential www.semtech.com 3. input/output circuits figure 3-1: input circuit figure 3-2: sq_adj circuit figure 3-3: output circuit figure 3-4: sleep, bypass, and gain_sel circuits figure 3-5: cd circuit figure 3-6: op_ctl 2.625k rc sdi sdi rc 2k 2k 2k vcc_a vcc_a vcc_a sq_adj 82.4k + - vcc_a 50 50 ddo ddo vcc_o vcc_o vcc_o sleep, bypass, gain_sel 100k vcc_a vcc_a cd internal 2.5v vcc_a vcc_a internal reference internal reference op_ctl internal circuitry 100k vcc_a
GS6042 final data sheet rev. 3 pds-060055 may 2014 11 of 21 proprietary and confidential www.semtech.com 4. detailed description the GS6042 is a high-speed bicmos ic designed to automatically equalize high-bandwidth serial digital video signals. the GS6042 can equalize data rates up to 6.25gb/s including 6g uhd-sdi, 3g sdi, hd sdi, and sd sdi serial digital signals. the gs 6042 is optimized to equalize up to 80m of belden 1694a cable at 5.94gb/s (uhd-sdi), 210m at 2.97gb/s (3g-sdi), 300m at 1. 485gb/ s (hd-sdi), and 500m at 270mb/s (sd-sdi). the GS6042 can be powered from a sing le +3.3v dc power supply, and is footprint-compatible with semtechs gs2974a, gs2974b, gs2984, gs2994, and gs3440 equalizers. 4.1 serial digital inputs the received serial data signal is connected to the input pins (sdi/sdi ) in either a differential or single-ended configuration. ac-coupling of the in puts is recommended because the sdi and sdi inputs are internally biased to approximately 1.71v. see figure 5-1 for the recommended input appl ications circuit when using a single-ended 75 coax cable. 4.2 automatic (adaptive) cable equalization the input signal passes through a variable gain equalizing stage, whose frequency response closely matches the inverse of the belden 1694a cable loss characteristic for any given attached cable length within the supported ranges. the equalized signal is dc-restored, effe ctively restoring the logic threshold of the equalized signal to its correct level in dependent of shifts due to ac-coupling. 4.3 differential digital data output the digital data output signals (ddo/ddo ) have a nominal output voltage swing of either 850mv ppd or 425mv ppd ( v ddo ), as set by the op_ctl pin. table 4-1 shows the typical output common mode voltage levels (v cmout ) related to the two output swing options and the type of output tran smission termination as shown in figure 4-1 and figure 4-2 .
GS6042 final data sheet rev. 3 pds-060055 may 2014 12 of 21 proprietary and confidential www.semtech.com 4.4 programmable squelch adjust (sq_adj) the GS6042 features a programmable squelch adjust (sq_adj) threshold. this feature can be useful in applications where there are multiple input channels using the GS6042 and the maximum gain of each device must be limite d to avoid crosstalk. the sq_adj pin acts to change the threshold of the carrier detect (cd ) pin. when the input signal level drops below th e threshold set by sq_adj, the cd pin will be driven high, indicating that there is not a valid input signal. this feature has been designed for use in applications such as routers, where signal crosstalk and circuit noise cause the equalize r to output erroneous data when no input signal is present. the use of a carrier detect function with a fixed in ternal reference does not solve this problem since the signal-to-noise ratio on the circuit board could be significantly less than the default signal detection leve l set by the on -chip reference. in applications where progra mmable squelch adjust is not required, the sq_adj pin can be left unconnected. note : when using sq_adj to limit th e maximum gain of the GS6042, cd should not be connected to sleep. table 4-1: typical common mode output voltage levels (v cmout ) supply voltage (vcc_o) termination type 1 (see figure 4-1 ) (see 1 ) termination type 2 (see figure 4-2 ) 425mv ppd swing 850mv ppd swing 425mv ppd swing 850mv ppd swing 3.3v 3.19v 3.09v 3.09v 2.88v 2.5v 2.39v 2.29v 2.29v 2.08v 1.8v 1.69v 1.59v 1.59v 1.38v 1.2v 1.09v 0.99v 0.99v 0.78v note: 1. the values shown for termination type 1 only apply when v term = vcc_o figure 4-1: 50 termination to v term figure 4-2: 100 parallel output termination 50 50 ddo ddo vcc_o 50 50 dd o dd o v cc_o 50 50 GS6042 v term v term 50 50 50 50 ddo ddo vcc_o 50 50 dd o dd o v cc_o 100 GS6042 50 50
GS6042 final data sheet rev. 3 pds-060055 may 2014 13 of 21 proprietary and confidential www.semtech.com 4.5 carrier detect, sleep, and auto-sleep the carrier detect output pin (cd ) indicates the presence of a valid signal at the input of the GS6042. when cd is low, the device has detect ed a valid input on sdi/sdi . when cd is high, the device considers the input invalid. note 1: cd will only detect loss of signal for data rates greater than 19mb/s. note 2: if sq_adj is being used to limit th e maximum gain of the device, and the maximum cable length is exceeded, the cd pin will be set to high even if an input is present. the GS6042 also includes a sleep input pin, which can be used to put the device into a low-power sleep mode. in this mode, the outp uts are high impedance and will be pulled high by the on-chip termination. set the sl eep pin high to place the chip in this low-power state. in this mode, the carrier detect output will still function to facilitate the detection of a valid seri al input data signal. auto-sleep is enabled by connecting cd to sleep. when connec ted, the GS6042 will automatically go into low-power sleep mode when there is a loss of input signal. note 3: if the cd pin is connected to the sleep pin, sq_adj must be either left open, or connected to ground. 4.6 gain_sel the GS6042 provides the option of compensating for 6db of flat attenuation prior to the equalizer. table 4-2: cd output cd input status 0 valid input on sdi/sdi pins 1 input is not valid table 4-3: sleep input sleep function 0 normal operation 1 low-power sleep mode; cd output remains valid table 4-4: gain_sel input table gain_sel function 0 no flat band gain is applied 1 6db of flat band gain applied to input signal
GS6042 final data sheet rev. 3 pds-060055 may 2014 14 of 21 proprietary and confidential www.semtech.com 4.7 adjustable output swing, de-emphasis, and mute the op_ctl input pin determines the outp ut swing and de-emphasis settings for ddo and ddo . the op_ctl pin is an analog input, allowing different combinations of output swing, de-emphasis, and mute. the po ssible values are listed in table 4-5 . when muted, the output swing is set to 425mv ppd and the output s are latched. automatic muting of the output ca n be enabled by connecting the cd pin to the op_ctl pin. if the connection is made directly, as shown in figure 4-3 , the output would be in its default mode (850mv ppd swing with no de-emphasis) when there is signal present. figure 4-3: direct loopback to enable automatic muting wh ile the output is configured for other settings, a resistor network can be used between cd and vcc_a. the intermediate voltages of this resistor ladder can set the output to any one of the nine different settings as shown in the examples given in figure 4-4 and figure 4-5 . table 4-5: op_ctl functions and levels level swing de-emphasis mute voltage (v) 0 850mv ppd off n 0.000 - 0.083 1 850mv ppd 2db n 0.234 - 0.394 2 850mv ppd 6db n 0.545 - 0.704 3 850mv ppd 8db n 0.856 - 1.015 4 425mv ppd off n 1.166 - 1.333 5 425mv ppd 2db n 1.484 - 1.644 6 425mv ppd 6db n 1.795 - 1.954 7 425mv ppd 8db n 2.106 - 2.265 8 425mv ppd n/a y 2.416 - 2.500 op_ctl cd
GS6042 final data sheet rev. 3 pds-060055 may 2014 15 of 21 proprietary and confidential www.semtech.com in figure 4-4 , the automatic muting of the output is established by connecting node 3 to the op_ctl pin. in this scen ario, the output would be 850mv ppd with 8db of de-emphasis when there is a signal present. in figure 4-5 , the op_ctl pin is connected to node 4. in this scenario, the output would be 425mv ppd with no de-emphasis when there is a signal present. in both cases, the output would be muted when no carrier is detected. note: when the device is in sleep mode, automatic muti ng and sq_adj do not function. asserting the sleep pin manually overrides all other functionality. figure 4-4: resistor divi der loopback example #1 (function level 3 from table 4-5 ) figure 4-5: resistor divider loopback example #2 (function level 4 from table 4-5 ) cd op_ctl vcc_a 1k 1k 1k 1k 1k 1k 1k 1k 2.6k 012345678 levels taps cd op_ctl vcc_a 1k 1k 1k 1k 1k 1k 1k 1k 2.6k 012345678 levels taps
GS6042 final data sheet rev. 3 pds-060055 may 2014 16 of 21 proprietary and confidential www.semtech.com 5. application information 5.1 high-gain adaptive cable equalizers the GS6042 is a multi-rate adaptive cable equali zer. in order to extend the cable lengths that the device can support, it is necessary to have high-gain in the equalizer. in particular, an sdi video cable equalizer must provide wide band gain over a range of frequencies in order to accommodate the range of data rates and signal patterns that are present in a smpte-compliant serial video stream. small levels of signal or noise present at the input pins of the equalizer may cause chatter at the output. in order to prevent this from happe ning, particular attention must be paid to board layout. 5.2 pcb layout special attention must be paid to component la yout when designing serial digital interfaces for hdtv and other high-s peed video applications. an fr-4 dielectric can be used, however, cont rolled impedance transmissi on lines are required for pcb traces longer than approximately 1cm. note the following pcb artwork features used to optimize performance: ? pcb trace width for high data rate signals should be closely matched to smt component width to minimize reflections due to changes in trace impedance ? high-speed traces should be curved to minimize impedance changes ? cutouts in the inner layers should be used under the GS6042 input and output components to minimize parasitic capacitance
GS6042 final data sheet rev. 3 pds-060055 may 2014 17 of 21 proprietary and confidential www.semtech.com 5.3 typical application circuit figure 5-1: GS6042 typical application circuit recommended for extended cable reach applications figure 5-2: GS6042 alternate application circuit recommended for drop in replacement applications 1 4 5 6 2 3 8 7 12 11 14 15 9 75 1f 1f GS6042 37.5 68.1 6.2nh* op_ctl ddo ddo sq_adj bypass sdi sdi vcc_a 4.7f 470nf center pad cd sleep vee_o agc agc gain_sel vee_a 0** sdi *value dependent on layout **this is a placeholder to allow for flexibility in the termination circuit population. it can be populated with 0w by default. vcc_o 10nf 13 16 vcc_a vcc_o 10 4.7f 10nf 75 6.2nh 7 10 1f 470nf 4 14 12 1 13 16 8 2 3 9 11 15 6 5 37.4 1f 10nf vcc_a 4.7f 75 vcc_o 4.7f GS6042 op_ctl ddo ddo sq_adj bypass sdi sdi vcc_a center pad cd sleep vee_o agc agc gain_sel vee_a vcc_o 10nf
GS6042 final data sheet rev. 3 pds-060055 may 2014 18 of 21 proprietary and confidential www.semtech.com 6. package & ordering information 6.1 package dimensions 6.2 packaging data 4.00 4.00 a b c datum a datum b 2.600.10 2.600.10 0.10 m cab 0.10 m cab detail a 0.30@45 r0.30 (3x) pin 1 area 0.15 c 0.15 c 0.10 c 0.08 c 16x seating plane 2x 2x 0.20 ref 0.900.10 0.02 +0.03 -0.02 0.10 m cab 0.05 m c 0.400.05 0.300.05 datum a or b 16x 0.65 0.65/2 detail a (scale 3:1) notes: 1. dimensioning and tolerance is in conformance to asme y14.5-1994 all dimensions are in millimeters in degrees 2. dimension of lead width applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip (both rows). if the terminal has optional radius on the end of the terminal, the lead width dimension should not be measured in that radius area parameter value package type 4mm x 4mm 16-pin qfn package drawing reference jedec m0220 moisture sensitivity level 1 junction to case thermal resistance, j-c 31.0c/w junction to air thermal resistance, j-a (at zero airflow) 43.8c/w psi, 11.0c/w pb-free and rohs compliant yes
GS6042 final data sheet rev. 3 pds-060055 may 2014 19 of 21 proprietary and confidential www.semtech.com 6.3 recommended pcb footprint the center pad should be connected to the most negative power supply plane for analog circuitry in the device (vee_a) by a minimum of 5 vias. note: suggested dimensions only. final dimensions should conform to customer design rules and process optimizations. 6.4 marking diagram 0.30 0.55 2.60 3.70 2.60 3.70 note: all dimensions are in millimeters. 0.65 center pad GS6042 xxxxe3 yyww pin 1 id xxxx - last 4 digits (excluding decimal) of sap batch assembly (fin) as listed on packing slip. e3 - pb-free & green indicator yyww - date code
GS6042 final data sheet rev. 3 pds-060055 may 2014 20 of 21 proprietary and confidential www.semtech.com 6.5 solder reflow profiles the GS6042 is available in a pb-free package. it is recommended that the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 6-1 . figure 6-1: maximum pb-free solder reflow profile 6.6 ordering information 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max part number package temperature range GS6042-ine3 16-pin qfn -40c to +85c
? semtech 2013 all rights reserved. reproduction in whole or in part is prohib ited without the prior written consent of the copyright owner. t he information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any licens e under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum rati ngs or operation outside the specified range. semtech products are not designed, intended, author ized or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized ap plication, the customer shall indemnify and hold semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fee s which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners . document identification final data sheet the product is in production. semtech reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GS6042 final data sheet rev. 3 pds-060055 may 2014 21 of 21 21 proprietary and confidential contact information semtech corporation 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111, fax: (805) 498-3804 www.semtech.com caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation

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